############## Modelsim simulation script #############################

# close last simulation
quit -sim

#set global variable
set root				d:/test
set vendor_lib	        $root/Lib/Xilinx_Lib
set user_lib		    $root/My_lib
set prj_dir		        $root/jrmoc_cmos
set sim_dir		        $prj_dir/simulation
set src_code		    $prj_dir/src

cd $sim_dir 

# create lib
if {![file exists work]} {
	cd $sim_dir
	vlib work
}

# map lib
vmap work 					work
vmap secureip				$vendor_lib/secureip
vmap unimacro_ver           $vendor_lib/unimacro_ver
vmap unisims_ver            $vendor_lib/unisims_ver
vmap xilinxcorelib_ver 		$vendor_lib/xilinxcorelib_ver


#Compile all rtl modules#
vlog  -incr	$src_code/ip/ddr_ctrl/*.v
vlog  -incr	$src_code/ip/ddr_ctrl/mcb_controller/*.v
vlog  -incr	$src_code/ip/RAM/*.v
vlog  -incr	$src_code/ip/FIFO/*.v
vlog  -incr	$src_code/ip/sobel/*.v

#Compile files in src folder (excluding model parameter file)#
vlog  -incr	$src_code/*.v
vlog  -incr	$sim_dir/*.v
vlog  -incr	$sim_dir/bfm/*.v

#Pass the parameters for memory model parameter file#
vlog  +incdir+. +define+x512Mb +define+sg25E +define+x16 $sim_dir/ddr2_model_c1.v

#Load the design. Use required libraries.#
vsim -t ps -novopt +notimingchecks -L unisims_ver -L secureip -L xilinxcorelib_ver work.cmos_tb glbl

#add wave
view wave
do wave.do

#run 
run -all